V61C5181024-12R 查看數據表（PDF） - Mosel Vitelic, Corp
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V61C5181024-12R Datasheet PDF : 12 Pages
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MOSEL VITELIC
Pin Descriptions
A0–A16 Address Inputs
These 17 address inputs select one of the 128K x 8
bit segments in the RAM.
CE1, CE2 Chip Enable Inputs
CE1 is active LOW and CE2 is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
V61C5181024
WE
Write Enable Input
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.
I/O0–I/O7 Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
VCC
GND
Power Supply
Ground
Pin Configurations (Top View)
32-Pin SOJ
NC 1
A10
2
A9
3
A8
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2
10
A1
11
A0
12
I/O0 13
I/O1 14
I/O2 15
GND 16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
5181024 02
VCC
A11
CE2
WE
A12
A13
A14
A15
OE
A16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A15
A14
A13
A12
WE
CE2
A11
VCC
NC
A10
A9
A8
A7
A6
A5
A4
32-Pin TSOP-I (Standard)
1
32
OE
2
31
A16
3
30
CE1
4
29
I/O7
5
28
I/O6
6
27
I/O5
7
26
I/O4
8
25
I/O3
9
24
VSS
10
23
I/O2
11
22
I/O1
12
21
I/O0
13
20
A0
14
19
A1
15
18
A2
16
17
A3
3181024 03
V61C5181024 Rev. 1.1 July 1998
2
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