GLT5160L16I-6TC 查看數據表（PDF） - G-Link Technology
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GLT5160L16I-6TC Datasheet PDF : 45 Pages
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FUNCTIONAL BLOCK DIAGRAM
A[10:0]
BA
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMU
Address Buffer
Clock Buffer
Control
Signal Buffer
Mode
Register
Memory Array
Bank #0
Memory Array
Bank #1
I/O Buffer
DQ[15:0]
Figure 1. 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
Signal Description
CLK
CKE
Signal
CS
RAS, CAS, WE
A[10:0]
BA
DQ[15:0]
DQML
DQMU
VDD, VSS
VDDQ, VSSQ
Type
Input
Input
Input
Input
Input
Input
Input / Output
Input
Input
Power Supply
Power Supply
Description
Master Clock: All other inputs are referenced to the rising edge of CLK.
Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased.
CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
Chip Select: When CS is high, any command means No Operation.
Combination of RAS, CAS, WE defines basic commands.
A[10:0] specify the Row / Column Address in conjunction with BA. The Row Address is specified by A[10:0].
The Column Address is specified by A[7:0]. A[10] is also used to indicate precharge option. When A[10] is
high at a read / write command, an auto precharge is performed. When A[10] is high at a precharge command,
both banks are precharged.
Bank Address: BA is not simply A[11]. BA specifies the bank to which a command is applied. BA must be set
with ACT, PRE, READ, WRITE commands.
Data In and Data out are referenced to the rising edge of CLK.
Lower Din[7:0] Mask / Lower Output[7:0] Disable: When DQML is high in burst write, lower Din[7:0] for the
current cycle is masked. When DQML is high in burst read, lower Dout[7:0] is disabled at the next but one
cycle.
Upper Din[15:8] Mask / Upper Output[15:8] Disable: When DQMU is high in burst write, upper Din(8-15) for
the current cycle is masked. When DQMU is high in burst read, upper Dout[15:8] is disabled at the next but
one cycle.
Power Supply for the memory array and peripheral circuitry.
VDDQ and VSSQ are supplied to the Output Buffers only.
2
G-LINK Technology
DEC. 2003 (Rev. 2.4)
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