GS88037BT-150 查看數據表（PDF） - Giga Semiconductor

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GS88037BT-150

256K x 36 9Mb Sync Burst SRAM

Giga Semiconductor 

TQFP Pin Description

Symbol

Type

A0, A1

I

A2–A17

I

A18

I

DQA1–DQA9

DQB1–DQB9

DQC1–DQC9

I/O

DQD1–DQD98

NC

—

BW

I

BA, BB

I

BC, BD

I

CK

I

GW

I

E1, E3

I

E2

I

G

I

ADV

I

ADSP, ADSC

I

ZZ

I

LBO

I

VDD

I

VSS

I

VDDQ

I

VDDQ/DNU

—

Preliminary

GS88037BT-333/300/275/250/225/200

Description

Address field LSBs and Address Counter preset Inputs

Address Inputs

Address Input

Data Input and Output pins

No Connect

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQA, DQB Data I/Os; active low

Byte Write Enable for DQC, DQD Data I/Os; active low

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Linear Burst Order mode; active low

Core power supply

I/O and Core Ground

Output driver power supply

VDDQ or VDD (must be tied high)

or

Do Not Use (must be left floating)

Rev: 1.00b 12/2002

3/19

© 2002, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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