LSM330DL 查看數據表（PDF） - STMicroelectronics
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LSM330DL Datasheet PDF : 54 Pages
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Module specifications
LSM330DL
2.4
Communication interface characteristics
2.4.1 SPI - serial peripheral interface
The values given in the following table are subject to the general operating conditions for
Vdd and TOP.
Table 6. SPI slave timing values
Symbol
Parameter
Value(1)
Min
Max
Unit
tc(SPC)
SPI clock cycle
100
ns
fc(SPC)
SPI clock frequency
10
MHz
tsu(CS)
CS setup time
6
th(CS)
CS hold time
8
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
ns
tv(SO)
SDO valid output time
50
th(SO)
SDO output hold time
9
tdis(SO)
SDO output disable time
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
Figure 3. SPI slave timing diagram (b)
CS (3)
SPC (3)
tsu(CS)
SDI (3)
SDO (3)
tc(SPC)
tsu(SI)
th(SI)
MSB IN
tv(SO)
MSB OUT
th(SO)
(3)
th(CS)
(3)
LSB IN
(3)
tdis(SO)
LSB OUT
(3)
3. Data on CS, SPC, SDI and SDO concern the following pins: CS_A/G, SCL_A/G, SDA/SDI_A/G, SDO_A/G
b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
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Doc ID 022018 Rev 1
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