MAX2741(2005) 查看數據表（PDF） - Maxim Integrated

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MAX2741
(Rev.:2005)

Integrated L1-Band GPS Receiver

Maxim Integrated 

Integrated L1-Band GPS Receiver

VCC4 6

GND

7

MAX2741

89

22nF

36kΩ

100pF

Figure 1. Recommended 3rd-Order PLL Filter

The VCO offers a bank of tuning capacitors that can be

latched in/out to adjust the center frequency. Because

the system does not require any RF LO frequency

change (i.e., changing channels), the VCO varactor tun-

ing gain is very low by design, which means the tuning

range of the VCO is narrow. The coarse-tune capacitors

in the tank circuit allow the system to adjust the VCO

center frequency as needed to guarantee that the syn-

thesizer can lock. In practice, process and temperature

effects on VCO centering are negligible, and a coarse-

tune setting of 110 (CONFIG:D7 to D5) will center the

VCO tuning range correctly in virtually all cases. To aid in

bench and prototype testing, the PFD offers out-of-lock-

high and out-of-lock-low indicators, available in the SPI

STATUS register (STATUS:D9 to D8). Use these flags to

determine if the VCO tuning range needs to be adjusted

higher or lower in the case where the PLL cannot lock.

The PLL filter is the only external block of the synthesizer.

The typical filter is a classic C-R-C two-pole shunt network

on the tune line. Low phase noise is preferred at the

expense of longer PLL settling times, so a low 10kHz to

20kHz loop bandwidth is used. The recommended PLL

10kHz filter implementation, with charge pump set to

200µA (CONFIG1:D10 = 1), is shown in Figure 1.

The system/GPS clock is derived either directly from

the reference oscillator, or synthesized from the RFLO

(see the ADC section). This clock is used as the sam-

pling clock for the on-chip ADC, and is seen at pin 15,

GPSCLK.

SPI Bus, Address and Bit Assignments

An SPI-compatible serial interface is used to program the

MAX2741 for configuring the different operating modes.

In addition, data can be read out of the MAX2741 for sta-

tus and diagnostic use. The serial interface is controlled

by four signals: SCLK (serial clock), CS (chip-select), SDI

(data input), and SDO (data output).

The control of the PLL, AGC, test, offset management,

and block selection is performed through the SPI bus

from the baseband controller. A 20-bit word, with the MSB

(D15) being sent first, is clocked into a serial shift register

when the chip-select signal is asserted low.

The SPI bus has four control lines: serial clock (SCLK),

chip-select (CS), data in (SDI), and data out (SDO).

Enable SDO functionality by setting the digital test bus

bits: CONFIG1:D9 to D8 = 01. The timing of the inter-

face signals is shown in Figure 2 and Table 1 along

with typical values for setup and hold time require-

ments.

For best performance, the SPI bus should be configured

during the startup initialization and then left with the opti-

mum values in the registers. Any changes to the ADC

and VGA bits during GPS signal processing may cause

glitches and corrupt the analog signal path. Reading

from the SPI bus does not interrupt GPS operation.

CS

SCLK

SDI

tSETUPD

tHDATA

LSB

tPERIOD

MSB

tSETUPSS

tEND

Figure 2. SPI Timing Diagram

Table 1. SPI Timing Requirements

SYMBOL

tSETUPD

tPERIOD

tHDATA

tSETUPSS

tEND

PARAMETER

Data to SCLK setup

SCLK period

Data hold to SCLK

CS to SCLK disable

Falling SCLK to CS inactive

TYP

VALUE

20

100

20

20

20

UNITS

ns

ns

ns

ns

ns

6 _______________________________________________________________________________________

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