MAX458 查看數據表（PDF） - Maxim Integrated
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MAX458 Datasheet PDF : 16 Pages
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8x4 Video Crosspoint Switches with Buffers
_______________Detailed Description
Analog Section
The MAX458/MAX459 video crosspoint switches consist
of a high-speed 32 (8x4) switch array with wide-band-
width line drivers (Figure 1). This design allows make-
before-break switching to reduce output noise and
glitches, but the inputs will not short together. It also pro-
vides high input impedance and low input capacitance,
so no input buffer amplifier is needed. However,
because different transistors provide gain depending on
the input selection, the DC offset voltage shifts slightly
when a new input is switched in. The change in offset
voltage is typically 3mV.
All output buffers will drive back-terminated 50Ω, 75Ω,
or higher impedance lines with up to 100pF capaci-
tance. The amplifier outputs can be disabled, which is
useful for creating large arrays. When disabled, the
MAX458 presents an output impedance of approxi-
mately 1MΩ. The MAX459 disabled output impedance
is 1kΩ (to ground), due to the internal feedback resis-
tors used to achieve the gain of two.
During power-on, if C–—S– and –U—P—D—A—T—E– are held high, all
output amplifiers are disabled. In a large array, this
feature prevents two ON paralleled amplifiers from dis-
torting each other’s signals. The amplifiers can be pro-
grammed to come up in any state simultaneously at any
time after power-on. See the Creating Large Arrays
section.
1
19
SHUTDOWN
20
DIN
SHDN
DOUT
CS
SCLK
UPDATE
WR
CE
MAX458
MAX459
A0
A1
D0
D1
D2
D3
40 VCC
39
38 UPDATE
37 WRITE
36 CHIP ENABLE (SELECT)
26 AMPLIFIER SELECT A0
25 AMPLIFIER SELECT A1
24 DATA BIT D0
23 DATA BIT D1
22 DATA BIT D2
21 DATA BIT D3
Pin numbers apply to DIP package.
Figure 3. Parallel Connection (only logic pins shown)
Digital Section—Parallel Mode
The MAX458/MAX459 have two register banks—an
input register and a switch register (Figure 2). Each of
these registers is either latched (when the control input
iTs–Cs—ehE–leheaicgirntheep)dluootbwrry,etrttgahhineesstiedpnreapcriuseotndcrteeo(gnwoitsfrhtoeeAllnr0esdtaehnlebedycctAo–eW—1ndR.–trboIayflnbiAdno0pt–Chu—atE–n–Wi—dsaR–nAloda1wniid)ss.
transparent, and the state of D0–D3 is presented to the
switch register. The other
latched. If D0–D3 change
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(bgeoleastclhoewd),inthteheneswwidtcahtare(gthisetecrh. aInf g–W—eRd–
oDr0C––—DE– 3is)
will then
high, all
input registers are latched and their data is presented
Table 1. Amplifier Selection
A1
A0
Output Amplifier Selected
L
L
0
L
H
1
H
L
2
H
H
3
Table 2. Input Selection
D3 D2 D1 D0
Input Channel Selected
L
L
L
L
0
L
L
L
H
1
L
L
H
L
2
L
L
H
H
3
L
H
L
L
4
L
H
L
H
5
L
H
H
L
6
L
H
H
H
7
H
X
X
X
Disable output amplifier
selected by A0, A1.
Table 3. Writing Data
–C—E– –W—R– –U—P—D—A—T—E–
FUNCTION
HX
XH
H
Device not selected or is operating in seri-
H
al mode. Both registers are latched.
HX
XH
L
L
Data in input registers passes through
switch registers. Output reflects data in
input registers.
LL
Input register of selected amplifier is trans-
H
parent. Switch registers are latched. Other
input registers are latched.
LL
All switch registers and selected input regis-
ter are transparent. Selected amplifier (cho-
L
sen by state of A0, A1) reflects input data.
Other amplifiers reflect data that had been
latched into the input registers previously.
_______________________________________________________________________________________ 9
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