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9517A

Level translating I2C-bus repeater

NXP Semiconductors. 

NXP Semiconductors

PCA9517A

Level translating I2C-bus repeater

When port A of the PCA9517A is pulled LOW by a driver on the I2C-bus, a comparator

detects the falling edge when it goes below 0.3VCC(A) and causes the internal driver on

port B to turn on, causing port B to pull down to about 0.5 V. When port B of the

PCA9517A falls, first a CMOS hysteresis type input detects the falling edge and causes

the internal driver on port A to turn on and pull the port A pin down to ground. In order to

illustrate what would be seen in a typical application, refer to Figure 9 and Figure 10. If the

bus master in Figure 5 were to write to the slave through the PCA9517A, waveforms

shown in Figure 9 would be observed on the A bus. This looks like a normal I2C-bus

transmission except that the HIGH level may be as low as 0.9 V, and the turn on and turn

off of the acknowledge signals are slightly delayed.

On the B bus side of the PCA9517A, the clock and data lines would have a positive offset

from ground equal to the VOL of the PCA9517A. After the eighth clock pulse, the data line

will be pulled to the VOL of the slave device which is very close to ground in this example.

At the end of the acknowledge, the level rises only to the LOW level set by the driver in the

PCA9517A for a short delay while the A bus side rises above 0.3VCC(A) then it continues

HIGH. It is important to note that any arbitration or clock stretching events require that the

LOW level on the B bus side at the input of the PCA9517A (VIL) be at or below 0.4 V to be

recognized by the PCA9517A and then transmitted to the A bus side.

Multiple PCA9517A port A sides can be connected in a star configuration (Figure 6),

allowing all nodes to communicate with each other.

Multiple PCA9517As can be connected in series (Figure 7) as long as port A is connected

to port B. I2C-bus slave devices can be connected to any of the bus segments. The

number of devices that can be connected in series is limited by repeater

delay/time-of-flight considerations on the maximum bus speed requirements.

PCA9517A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4.1 — 24 May 2016

© NXP Semiconductors N.V. 2016. All rights reserved.

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