SII161A 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

比赛名单

SII161A

PanelLink® Receiver

Unspecified 

Silicon Image, Inc.

Timing Diagrams

SiI 161A

SiI 161A

2.0 V

2.0 V

10pF

0.8 V

DLHT

Figure 1. Digital Output Transition Times

0.8 V

DHLT

SiI-DS-0009-D

2.0 V

RCIH

RCIP

2.0 V

2.0 V

0.8 V

0.8 V

RCIL

Figure 2. Receiver Clock Cycle/High/Low Times

RX0

RX1

RX2

VDIFF=0V

TCCS

VDIFF=0V

Figure 3. Channel-to-Channel Skew Timing

Output Timing

ODCK_INV = 1

ODCK_INV = 0

QE[23:0]/QO[23:0],

DE, HSYNC, VSYNC,

CTL[3:1]

TSetup

T Hold

Figure 4. Output Data, DE, and Control Signals Setup/Hold Times to ODCK Falling Edge when ODCK_INV=0, or ODCK

Rising Edge when ODCK_INV = 1.

Silicon Image, Inc.

7

Subject to Change without Notice

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