GS82032AT-150 查看數據表（PDF） - Giga Semiconductor

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GS82032AT-150

64K x 32 2Mb Synchronous Burst SRAM 180 MHz–66 MHz 3.3 V VDD 3.3 V and 2.5 V I/O

Giga Semiconductor 

GS82032AT-180/166/150/133/100/66/4/5/6

Simplified State Diagram with G

X

Deselect

W

R

W

R

X

First Write R

CW

CR

W

First Read X

CW

CR

W

X

R

Burst Write

CR

CW

R

W

Burst Read X

CW

CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G high) may be used to make the transition from Read cycles to Write cycles without passing

through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.

3. Transitions shown in gray assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data

Input Set Up Time.

Rev: 1.12 10/2004

9/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2000, GSI Technology

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