XRT83SL38 查看數據表（PDF） - Exar Corporation

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XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

Exar Corporation 

XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

REV. P1.1.0

PRELIMINARY

TABLE 7: RECEIVE TERMINATIONS ....................................................................................................... 32

Figure 12. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ............. 32

TRANSMITTER (CHANNELS 0 - 7) ............................................................................................................ 33

Transmit Termination Mode .............................................................................................................................. 33

External Transmit Termination Mode ............................................................................................................... 33

Figure 13. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... 33

TABLE 8: TRANSMIT TERMINATION CONTROL ....................................................................................... 33

TABLE 9: TERMINATION SELECT CONTROL ........................................................................................... 33

REDUNDANCY APPLICATIONS ............................................................................................................. 34

TABLE 10: TRANSMIT TERMINATION CONTROL ..................................................................................... 34

TABLE 11: TRANSMIT TERMINATIONS ................................................................................................... 34

TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 35

Figure 14. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ....... 36

Figure 15. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy .............. 36

Figure 16. Simplified Block Diagram - Transmit Section for N+1 Redundancy ......................... 37

Figure 17. Simplified Block Diagram - Receive Section for N+1 Redundancy ........................... 38

PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... 39

TRANSMIT ALL ONES (TAOS) ..................................................................................................................... 39

NETWORK LOOP CODE DETECTION AND TRANSMISSION ............................................................................... 39

TABLE 12: PATTERN TRANSMISSION CONTROL ...................................................................................... 39

TABLE 13: LOOP-CODE DETECTION CONTROL ..................................................................................... 39

TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... 40

LOOP-BACK MODES .................................................................................................................................... 41

TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE ........................................................................ 41

TABLE 15: LOOP-BACK CONTROL IN HOST MODE .................................................................................. 41

LOCAL ANALOG LOOP-BACK (ALOOP) ........................................................................................................ 42

REMOTE LOOP-BACK (RLOOP) .................................................................................................................. 42

Figure 18. Local Analog Loop-back signal flow ............................................................................ 42

Figure 19. Remote Loop-back mode with jitter attenuator selected in receive path ................. 42

DIGITAL LOOP-BACK (DLOOP) ................................................................................................................... 43

Figure 20. Remote Loop-back mode with jitter attenuator selected in Transmit path .............. 43

Figure 21. Digital Loop-back mode with jitter attenuator selected in Transmit path ................ 43

DUAL LOOP-BACK ...................................................................................................................................... 44

Figure 22. Signal flow in Dual loop-back mode ............................................................................. 44

MICROPROCESSOR PARALLEL INTERFACE .............................................................. 45

TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ........................................................... 45

MICROPROCESSOR REGISTER TABLES ........................................................................................................ 46

TABLE 17: MICROPROCESSOR REGISTER ADDRESS ............................................................................. 46

TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION .................................................................. 46

MICROPROCESSOR REGISTER DESCRIPTIONS .............................................................................................. 50

TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION ............................................................ 50

TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION ............................................................ 51

TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION ............................................................ 53

TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION ............................................................ 55

TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION ............................................................ 57

TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION ............................................................ 58

TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION ............................................................ 60

TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION ............................................................ 61

TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION ............................................................ 62

TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION ............................................................ 62

TABLE 29: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION .......................................................... 63

TABLE 30: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION .......................................................... 63

TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION .......................................................... 64

TABLE 32: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION .......................................................... 64

II

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