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L3GD20 查看數據表(PDF) - STMicroelectronics

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L3GD20 Datasheet PDF : 44 Pages
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L3GD20
7
Register description
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
angular rate data. The register address, consisting of 7 bits, is used to identify them and to
write the data through the serial interface.
7.1
WHO_AM_I (0Fh)
Table 17. WHO_AM_I register
1
1
0
1
0
1
0
0
Device identification register.
7.2
CTRL_REG1 (20h)
Table 18. CTRL_REG1 register
DR1
DR0
BW1
BW0
PD
Zen
Xen
Yen
Table 19.
DR1-DR0
BW1-BW0
CTRL_REG1 description
Output data rate selection. Refer to Table 20
Bandwidth selection. Refer to Table 20
Power-down mode enable. Default value: 0
PD
(0: power-down mode, 1: normal mode or sleep mode)
Zen
Z axis enable. Default value: 1
(0: Z axis disabled; 1: Z axis enabled)
Yen
Y axis enable. Default value: 1
(0: Y axis disabled; 1: Y axis enabled)
Xen
X axis enable. Default value: 1
(0: X axis disabled; 1: X axis enabled)
DR<1:0> is used for ODR selection. BW <1:0> is used for Bandwidth selection.
In the Table 20 all frequencies resulting in combinations of DR / BW bits are reported.
Table 20. DR and BW configuration setting
DR <1:0>
BW <1:0>
00
00
95
00
01
95
00
10
95
ODR [Hz]
Cut-Off
12.5
25
25
Doc ID 022116 Rev 1
31/44

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