2SJ280L 查看數據表（PDF） - Hitachi -> Renesas Electronics

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产品描述 (功能)

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2SJ280L

Silicon P Channel MOS FET

Hitachi -> Renesas Electronics 

2SJ280 L , 2SJ280 S

Reverse Drain Current vs.

Source to Drain Voltage

–50

Pulse Test

–40

VGS= –10 V

–30

–20

–5 V

0, 5V

–10

0

0 –0.4 –0.8 –1.2 –1.6 –2.0

Source to Drain Voltage VSD (V)

Maxmum Avalanche Energy vs.

Channel Temperature Derating

100

I AP = –30 A

80

VDD = –25 V

duty < 0.1%

Rg >=50 Ω

60

40

20

0

25 50 75 100 125 150

Channel Temperature Tch (°C)

Vin

–15 V

VDS

Monitor

Rg

50 Ω

Avalanche Test Circuit and Waveform

L

I AP

Monitor

D.U.T

VDD

EAR =

1

2

• L • I AP 2 •

VDSS

VDSS – VDD

I AP

ID

V(BR)DSS

VDS

0 VDD

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