2SJ598 查看數據表（PDF） - NEC => Renesas Technology

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2SJ598

MOS FIELD EFFECT TRANSISTOR

NEC => Renesas Technology 

2SJ598

ELECTRICAL CHARACTERISTICS (TA = 25°C)

CHARACTERISTICS

SYMBOL

TEST CONDITIONS

Zero Gate Voltage Drain Current

Gate Leakage Current

Gate Cut-off Voltage

IDSS

IGSS

VGS(off)

VDS = –60 V, VGS = 0 V

VGS = m16 V, VDS = 0 V

VDS = –10 V, ID = –1 mA

Forward Transfer Admittance

| yfs | VDS = –10 V, ID = –6 A

Drain to Source On-state Resistance

RDS(on)1 VGS = –10 V, ID = –6 A

RDS(on)2 VGS = –4.0 V, ID = –6 A

Input Capacitance

Ciss

VDS = –10 V

Output Capacitance

Coss

VGS = 0 V

Reverse Transfer Capacitance

Crss

f = 1 MHz

Turn-on Delay Time

td(on)

ID = –6 A

Rise Time

tr

VGS = –10 V

Turn-off Delay Time

td(off)

VDD = –30 V

Fall Time

tf

RG = 0 Ω

Total Gate Charge

QG

ID = –12 A

Gate to Source Charge

QGS

VDD= –48 V

Gate to Drain Charge

QGD

VGS = –10 V

Body Diode Forward Voltage

VF(S-D) IF = 12 A, VGS = 0 V

Reverse Recovery Time

trr

IF = 12 A, VGS = 0 V

Reverse Recovery Charge

Qrr

di/dt = 100 A /µs

MIN.

–1.5

5

TYP. MAX.

–10

m10

–2.0 –2.5

11

102 130

131 190

720

150

50

7

4

35

10

15

3

4

0.98

50

100

UNIT

µA

µA

V

S

mΩ

mΩ

pF

pF

pF

ns

ns

ns

ns

nC

nC

nC

V

ns

nC

TEST CIRCUIT 1 AVALANCHE CAPABILITY

D.U.T.

RG = 25 Ω

L

PG.

50 Ω

VDD

VGS = −20 → 0 V

−

IAS BVDSS

VDS

ID

VDD

Starting Tch

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

RG

PG.

VGS(−)

0

τ

τ = 1 µs

Duty Cycle ≤ 1%

RL

VDD

VGS(−)

VGS

Wave Form

0 10%

VDS(−)

90%

VDS

VDS

Wave Form 0

td(on)

VGS

90%

90%

10% 10%

tr td(off)

tf

ton

toff

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

IG = −2 mA

RL

PG.

50 Ω

VDD

2

Data Sheet D14656EJ4V0DS

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