5962R9582401QQC(1996) 查看數據表（PDF） - Intersil

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5962R9582401QQC
(Rev.:1996)

Radiation Hardened 8-Bit CMOS Microprocessor

Intersil 

HS-80C85RH

TABLE 9. INSTRUCTION SET SUMMARY (Continued)

INSTRUCTION CODE

MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0

OPERATIONS

DESCRIPTION

JPE

1 1 1 0 1 0 1 0 Jump on parity

even

INSTRUCTION CODE

MNEMONIC D7 D6 D5 D4 D3 D2 D1 D0

OPERATIONS

DESCRIPTION

ADC M

1 0 0 0 1 1 1 0 Add memory to A

with carry

JPO

PCHL

1 1 1 0 0 0 1 0 Jump on parity odd

ADl

1 1 1 0 1 0 0 1 H & L to program

ACl

counter

1 1 0 0 0 1 1 0 Add immediate to A

1 1 0 0 1 1 1 0 Add immediate to A

with carry

CALL

DAD B

0 0 0 0 1 0 0 1 Add B & C to H & L

CALL

CC

1 1 0 0 1 1 0 1 Call unconditional

1 1 0 1 1 1 0 0 Call on carry

DAD D

DAD H

0 0 0 1 1 0 0 1 Add D & E to H & L

0 0 1 0 1 0 0 1 Add H & L to H & L

CNC

LOGICAL

ANA r

XRA r

ORA r

CMP r

ANA M

XRA M

ORA M

CMP M

ANI

XRI

ORl

CPl

1 1 0 1 0 1 0 0 Call on no carry

1 0 1 0 0 S S S And register with A

1 0 1 0 1 S S S Exclusive OR

register with A

1 0 1 1 0 S S S OR register with A

1 0 1 1 1 S S S Compare register

with A

1 0 1 0 0 1 1 0 And memory with A

1 0 1 0 1 1 1 0 Exclusive OR mem-

ory with A

1 0 1 1 0 1 1 0 OR memory with A

1 0 1 1 1 1 1 0 Compare memory

with A

1 1 1 0 0 1 1 0 And immediate

with A

1 1 1 0 1 1 1 0 Exclusive OR

immediate with A

1 1 1 1 0 1 1 0 OR immediate

with A

1 1 1 1 1 1 1 0 Compare immedi-

ate with A

DAD SP

SUBTRACT

SUB r

SBB r

SUB M

SBB M

SUl

SBl

SPECIALS

CMA

STC

CMC

DAA

CONTROL

0 0 1 1 1 0 0 1 Add stack pointer to

H&L

1 0 0 1 0 S S S Subtract register

from A

1 0 0 1 1 S S S Subtract register

from A with borrow

1 0 0 1 0 1 1 0 Subtract memory

from A

1 0 0 1 1 1 1 0 Subtract memory

from A with borrow

1 1 0 1 0 1 1 0 Subtract immedi-

ate from A

1 1 0 1 1 1 1 0 Subtract immedi-

ate from A with

borrow

0 0 1 0 1 1 1 1 Complement A

0 0 1 1 0 1 1 1 Set carry

0 0 1 1 1 1 1 1 Complement carry

0 0 1 0 0 1 1 1 Decimal adjust A

ROTATE

El

RLC

0 0 0 0 0 1 1 1 Rotate A left

DI

1 1 1 1 1 0 1 1 Enable Interrupts

1 1 1 1 0 0 1 1 Disable Interrupt

RRC

0 0 0 0 1 1 1 1 Rotate A right

NOP

0 0 0 0 0 0 0 0 No-operation

RAL

RAR

INX H

DCX B

DCX D

0 0 0 1 0 1 1 1 Rotate A left

through carry

0 0 0 1 1 1 1 1 Rotate A right

through carry

0 0 1 0 0 0 1 1 Increment H & L

registers

0 0 0 0 1 0 1 1 Decrement B & C

0 0 0 1 1 0 1 1 Decrement D & E

HLT

0 1 1 1 0 1 1 0 Halt

RIM

0 0 1 0 0 0 0 0 Read Interrupt

Mask

SlM

0 0 1 1 0 0 0 0 Set Interrupt Mask

NOTES:

1. DDS or SSS: B000, C001, D010, E011, H100, L101, Memory 110, A111

2. Two possible cycle times (6/12) indicate instruction cycles dependent on condi-

tion flags.

DCX H

ADD

0 0 1 0 1 0 1 1 Decrement H & L

† All mnemonics copyrighted „ Intel Corporation 1976

ADD r

1 0 0 0 0 S S S Add register to A

ADC r

ADD M

1 0 0 0 1 S S S Add register to A

with carry

1 0 C 0 0 1 1 0 Add memory to A

Spec Number 518054

11

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