IZ4406 查看數據表（PDF） - Integral Corp.

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IZ4406

Intelligent 104-Bit EEPROM Counter for > 20000 Units with Security Logic

Integral Corp. 

Intelligent 104-Bit EEPROM Counter

for > 20000 Units with Security Logic

IZ4406

Features

• 104 x 1 bit organisation

• Three memory areas with special characteristics

(eg ROM, PROM, EEPROM)

• Maximum of 20480 count units

• Special security features

• Minimum of 104 write/erase cycles

• Data retention for minimum of ten years

• Contact configuration and serial interface

in accordance to ISO standard 7816-3

(synchronous transmission)

Pin Definitions and Functions

Card Contact

Symbol

Function

C7

I/O

Bidirectional data line (open drain)

Code entry on “Input” only for transport

C3

CLC

Clock input

C2

RST

Control input (reset)

C1

VCC

Supply voltage

C6

N.C.

Not connected

C5

GND

Ground

IZ4406 comes as an M1 wire-bonded module for embedding in plastic cards and as a die for customer

packaging

General Description

The chip contains an EEPROM/PROM of 88 bits, a mask ROM of 16 bits and a sequencing control with

security logic (cf block diagram, Fig. 1).

Memory (104 bits) is divided into the following functional areas

I

ROM

This area contains unalterable chip data (eg application, design status).

Part of the data is entered by way of a ROM mask and the remainder

when testing. Both parts are unalterable.

II

PROM

In this area the user can enter card data for a particular application. A

control flag can be set to safeguard this area against alteration.

III

PROM/EEPROM

This area contains the count data and stores the current count in

nonvolatile memory. The individual counter stages with carry can be

erased (ie EEPROM), only the uppermost counter stage not being

erasable (ie PROM).

Before the control flag is set, part of the EEPROM area contains a secret

transport code. Another part serves as an error counter.

Function of the PROM area:

1 bit: Control flag

3 bits: Test bits for manufacturer

4 bits: for user

In the condition as supplied, the transport code and the error counter are activated. The chip can only be

read (except for the transport-code area) and only the error counter can be written.

Following correct entry of the transport code, the entire memory can be read and areas II and III can be

written and EEPROM part of area III can be erased.

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