74F350 查看數據表（PDF） - Fairchild Semiconductor

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74F350

4-Bit Shifter with 3-STATE Outputs

Fairchild Semiconductor 

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Pin Names

Description

S0, S1

I−3–I3

OE

O0–O3

Select Inputs

Data Inputs

Output Enable Input (Active LOW)

3-STATE Outputs

U.L.

HIGH/LOW

1.0/2.0

1.0/2.0

1.0/2.0

150/40 (33.3)

Input IIH/IIL

Output IOH/IOL

20 µA/−1.2 mA

20 µA/−1.2 mA

20 µA/−1.2 mA

−3 mA/24 mA (20 mA)

Functional Description

The 74F350 is operationally equivalent to a 4-input multi-

plexer with the inputs connected so that the select code

causes successive one-bit shifts of the data word. This

internal connection makes it possible to perform shifts of 0,

1, 2 or 3 places on words of any length.

A 4-bit data word is introduced at the In inputs and is

shifted according to the code applied to the select inputs

S0, S1. Outputs O0–O3 are 3-STATE, controlled by an

active LOW output enable (OE). When OE is LOW, data

outputs will follow selected data inputs; when HIGH, the

data outputs will be forced to the high impedance state.

This feature allows shifters to be cascaded on the same

output lines or to a common bus. The shift function can be

logical, with zeros pulled in at either or both ends of the

shifting field; arithmetic, where the sign bit is repeated dur-

ing a shift down; or end around, where the data word forms

a continuous loop.

Logic Equations

O0 = S0S1I0 + S0S1I−1 + S0S1I−2 + S0S1I−3

O1 = S0S1I1 + S0S1I0 + S0S1I−1 + S0S1I−2

O2 = S0S1I2 + S0S1I1 + S0S1I0 + S0S1I−1

O3 = S0S1I3 + S0S1I2 + S0S1I1 + S0S1I0

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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