74HC3G34 查看數據表（PDF） - Philips Electronics
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74HC3G34 Datasheet PDF : 16 Pages
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Philips Semiconductors
Triple buffer gate
Product specification
74HC3G34; 74HCT3G34
FEATURES
• Wide supply voltage range from 2.0 to 6.0 V
• Symmetrical output impedance
• High noise immunity
• Low power dissipation
• Balanced propagation delays
• Very small 8-pin package
• Output capability: standard
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74HC3G/HCT3G34 is a high-speed Si-gate CMOS
device and is pin compatible with low power Schottky TTL
(LSTTL). Specified in compliance with JEDEC
standard no. 7.
The 74HC3G/HCT3G34 provides three buffers.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH propagation delay nA to nY
CI
input capacitance
CPD
power dissipation capacitance per gate
CL = 50 pF;
VCC = 4.5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
∑ (CL × VCC2 × fo) = sum of outputs.
2. For 74HC3G34 the condition is VI = GND to VCC.
For 74HCT3G34 the condition is VI = GND to VCC − 1.5 V.
TYPICAL
HC3G34 HCT3G34
UNIT
9
10
ns
1.5
1.5
pF
10
9
pF
FUNCTION TABLE
See note 1.
INPUT
nA
L
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
2003 May 19
OUTPUT
nY
L
H
2
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