74LV595 查看數據表（PDF） - Philips Electronics

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74LV595

8-bit serial-in/serial or parallel-out shift register with output latches (3-State)

Philips Electronics 

Philips Semiconductors

8-bit serial-in/serial or parallel-out shift register

with output latches (3-State)

Product specification

74LV595

PIN DESCRIPTION

PIN

NUMBER

SYMBOL

FUNCTION

15, 1, 2, 3,

4, 5, 6, 7

Q0 to Q7 Parallel data output

8

GND Ground (0V)

9

Q7’

Serial data output

10

MR Master reset (active LOW)

11

SHCP Shift register clock input

12

STCP Storage register clock input

13

OE Output enable input (active LOW)

14

DS

Serial data input

16

VCC Positive supply voltage

FUNCTION TABLE

INPUTS

SHCP STCP OE

MR

DS

X

X

L

L

X

X

°

L

L

X

X

X

H

L

X

°

X

L

H

H

X

°

L

H

X

°

°

L

H

X

H = HIGH voltage level

L = LOW voltage level

X = Don’t care

Z = High impedance OFF-state

NC= No change

° = LOW-to-HIGH clock transition

↓ = HIGH-to-LOW transition

OUTPUTS

Q7’

Qn

L

NC

L

L

L

Z

Q6’

NC

NC

Qn’

Q6’

Qn’

PIN CONFIGURATION

Q1 1

Q2 2

Q3 3

Q4 4

Q5 5

Q6 6

Q7 7

GND 8

16 VCC

15 Q0

14 DS

13 OE

12 STCP

11 SHCP

10 MR

9 Q7’

SV00720

FUNCTION

A LOW level on MR only affects the shift registers

Empty shift register loaded into storage register

Shift register clear. Parallel outputs in high-impedance OFF-states

Logic high level shifted into shift register stage 0. Contents of all shift

register stages shifted through, e.g. previous state of stage 6 (internal

Q6’) appears on the serial output (Q7’)

Contents of shift register stages (internal Qn’) are transferred to the

storage register and parallel output stages

Contents of shift register shifted through. Previous contents of the shift

register are transferred to the storage register and the parallel output

stages

1998 Apr 20

3

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