74LV595DB 查看數據表（PDF） - Philips Electronics

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74LV595DB

8-bit serial-in/serial or parallel-out shift register with output latches (3-State)

Philips Electronics 

Philips Semiconductors

8-bit serial-in/serial or parallel-out shift register

with output latches (3-State)

Product specification

74LV595

AC WAVEFORMS

VM = 1.5V at VCC w 2.7V

VM = 0.5 * VCC at VCC t 2.7V

VOL and VOH are the typical output voltage drop that occur with the

output load.

VX = VOL + 0.3V at VCC ≥ 2.7V

VX = VOL + 0.1VCC at VCC < 2.7V

VY = VOH – 0.3V at VCCw 2.7V

VY = VOH – 0.1VCC at VCC < 2.7V

VI

CP INPUT

GND

VOH

Qn OUTPUT

VOL

1/fmax

VM

tW

tPHL

VM

tPLH

SV00718

Figure 1. Clock (SHCP) to output (Q7’), propagation delays, the

shift clock pulse width and the maximum shift clock frequency.

VI

SHCP INPUT

GND

VI

STCP INPUT

GND

VOH

Qn OUTPUT

VOL

VM

tsu

VM

tW

tPLH

VM

1/fmax

tPHL

VI

OE INPUT

GND

VCC

OUTPUT

LOW-to-OFF

OFF-to-LOW

VOL

VM

tPLZ

VX

tPHZ

tPZL

VM

tPZH

VOH

OUTPUT

VY

HIGH-to-OFF

OFF-to-HIGH

VM

GND

outputs

enabled

outputs

disabled

outputs

enabled

SV00344

Figure 3. 3-State enable and disable times for input OE.

VI

SHCP INPUT

VM

GND

tsu

tsu

VI

ÏÏÏÏ DS INPUT

VM

ÏÏÏÏÏÏÏÏ GND

ÏÏÏth ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏthÏÏÏ

vOH

Q7’ OUTPUT

VM

VOL

SV00722

Figure 4. Data set-up and hold times for the data input (DS).

SV00727

Figure 2. Storage clock (STCP) to output (Qn) propagation

delays, the storage clock pulse width and the shift clock to

storage clock set-up time.

1998 Apr 20

9

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