74LVC377 查看數據表（PDF） - Philips Electronics

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74LVC377

Octal D-type flip-flop with data enable; positive-edge trigger

Philips Electronics 

Philips Semiconductors

Octal D-type flip-flop with data enable;

positive-edge trigger

Product specification

74LVC377

AC CHARACTERISTICS

GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.

LIMITS

SYMBOL

PARAMETER

WAVEFORM

VCC = 3.3V ±0.3V

MIN TYP1 MAX

VCC = 2.7V

MIN TYP MAX

tPHL

Propagation delay

tPLH

CP to Qn

tW

Clock pulse width

HIGH or LOW

1

6.0

10.2

6.6

11.2

1

4

1.0

5

1.6

tsu

Set-up time

E to CP

2

4

2.3

5

2.9

th

Hold time

E to CP

2

0

–2.2

0

–2.8

tsu

Set-up time

Dn to CP

th

Hold time

Dn to CP

fmax

Maximum clock

pulse frequency

3

2

1.3

3

0

–1.2

1

125

3

1.8

0

–1.6

100

NOTE:

1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C.

UNIT

ns

ns

ns

ns

ns

ns

MHz

AC WAVEFORMS

VM = 1.5V at VCC w 2.7V.

VM = 0.5 VCC at VCC t 2.7V.

VOL and VOH are the typical output voltage drop that occur with the output load.

VI

CP INPUT

GND

VOH

Qn OUTPUT

VOL

1/fMAX

VM

tw

tPHL

VM

tPLH

VCC

ÉÉÉ ÉÉÉÉÉÉÉÉÉ EInput

ÉÉÉ ÉÉÉÉÉÉÉÉÉ GND

ÉÉÉ ÉÉÉÉÉÉÉÉÉ VCC

ÉÉÉ ÉÉÉÉÉÉÉÉÉ DnInput

ÉÉÉ ÉÉÉÉÉÉÉÉÉ GND

ÉÉÉ ÉÉÉÉÉÉÉÉÉ VCC

VM

tsu

th

STABLE

VM

tsu

th

tsu

th

tW

SW00078

CP Input

VM

Waveform 1. Clock (CP) to output (Qn) propagation delays the

clock pulse width and the maximum clock pulse frequency.

GND

NOTE: The shaded areas indicate when the input is permitted to change

for predictable output performance.

SY00061

Waveform 2. Data set-up and hold times from the data input

(Dn) and from the enable

input (E) to the clock (CP).

1998 Jul 29

5

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