Philips Semiconductors
Octal D-type flip-flop with data enable;
positive-edge trigger
Product specification
74LVC377
TEST CIRCUIT
Vcc
PULSE
GENERATOR
Vl
RT
VO
D.U.T.
Test Circuit for Outputs
S1
VS1
Open
GND
RL = 1k
CL= 50pF
RL = 1k
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
tW
VM
10%
VM
10%
tTHL (tf)
tTLH (tr)
90%
VM
90%
VM
tW
VM = 1.5V
Input Pulse Definition
90%
VI
0V
tTLH (tr)
tTHL (tf)
VI
10%
0V
SWITCH POSITION
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VS1
GND
VCC
< 2.7V
2.7–3.6V
≥ 4.5 V
VI
VCC
2.7V
VCC
VS1
2 < VCC
2 < VCC
2 < VCC
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of
pulse generators.
Waveform 3. Load circuitry for switching times.
SY00044
1998 Jul 29
6