74LVX573(2004) 查看數據表（PDF） - STMicroelectronics

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74LVX573
(Rev.:2004)

LOW VOLTAGE CMOS OCTAL D-TYPE LATCH (3-STATE NON INV.) WITH 5V TOLERANT INPUTS

STMicroelectronics 

74LVX573

Figure 2: Input Equivalent Circuit

Table 2: Pin Description

PIN N°

SYMBOL NAME AND FUNCTION

1

OE

3 State Output Enable

Input (Active LOW)

2, 3, 4, 5, 6, D0 to D7 Data Inputs

7, 8, 9

12, 13, 14,

15, 16, 17,

18, 19

Q0 to Q7 3-State Latch Outputs

11

LE

Latch Enable Input

10

GND Ground (0V)

20

t(s) Table 3: Truth Table

uc INPUTS

rod OE

LE

D

H

X

X

P L

L

X

te L

H

L

le L

H

H

so X : Don’t Care

b Z : High Impedance

* : Q Outputs are Latched at the time when the LE INPUT is taken low logic level

Obsolete Product(s) - O Figure 3: Logic Diagram

VCC

Positive Supply Voltage

OUTPUT

Q

Z

NO CHANGE*

L

H

This logic diagram has not be used to estimate propagation delays

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