74VHC595(2007) 查看數據表（PDF） - Fairchild Semiconductor

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74VHC595
(Rev.:2007)

8-Bit Shift Register with Output Latches

Fairchild Semiconductor 

Connection Diagram

Logic Symbol

IEEE/IEC

Pin Description

Pin Names

Description

SER

Serial Data Input

SCK

Shift Register Clock Input

(Active rising edge)

RCK

Storage Register Clock Input

(Active rising edge)

SCLR

Reset Input

G

3-STATE Output Enable Input

(Active LOW)

QA – QH

Q’H

Parallel Data Outputs

Serial Data Output

Truth Table

SER

X

X

X

L

H

X

RCK

X

X

X

X

X

↑

Inputs

SCK

X

X

X

↑

↑

X

SCLR

X

X

L

H

H

H

G

Function

H

QA thru QH 3-STATE

L

QA thru QH outputs enabled

L

Shift Register cleared: Q′H = 0

L

Shift Register clocked: QN = Qn-1, Q0 = SER = L

L

Shift Register clocked: QN = Qn-1, Q0 = SER = H

L Contents of Shift Register transferred to output latches

©1993 Fairchild Semiconductor Corporation

74VHC595 Rev. 1.2

2

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