70P2352-IGT 查看數據表（PDF） - Unspecified

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70P2352-IGT

Dual Channel OC-3/ STM1-E/ E4 LIU

Unspecified 

Plesiochronous Tx Serial Mode

Figure 3 represents a common condition where a

serial transmit clock is not available and/or the data

is not source synchronous to the reference clock

input. In this mode, the 78P2352 will recover a

transmit clock from the serial plesiochronous data

and bypass the internal FIFO and re-timing block.

This mode is commonly used for mezzanine cards,

modules, and any application where the reference

clock cannot always be synchronous to the transmit

source clock/data.

Reference

Clock

XO

Framer/

Mapper

CKREFP

NRZ

SIxDP/N

CMIxP/N

NRZ

140 / 155 MHz

TDK

SOxCKP/N 78P2352

SOxDP/N

RXxP/N

CMI

CMI

Coax

XFMR

Coax

XFMR

Figure 3: Plesiochronous; data only

(Tx CDR enabled, FIFO bypassed)

Synchronous Parallel Modes

In parallel modes, 4-bit CMOS data segments are

input to the chip with a 34.816MHz (E4 ÷ 4) or

38.88MHz (STM1 ÷ 4) synchronous clock. These

inputs are re-timed in a 4x8 clock decoupling FIFO

and then to a serializer for transmission. Because

the data is passed through the FIFO and re-timed

using a synthesized clock, the transmit nibble clock

and data for both channels must be source

synchronous to the provided reference clock.

For maximum compatibility with legacy ASICs, the

78P2352 can operate in both slave and master clock

modes as shown in Figures 4 and 5 respectively.

Note: A loop-timing mode is also available to

allow external remote loopbacks (i.e. line

loopback in framer). In this mode, the FIFO is

still enabled, but the transmit data will be re-

timed using the recovered receive clock

Parallel

Mode

HW Control Pins

SDI_PAR CKMODE

SW Control Bits

PAR

PMODE

Slave

High

Low

1

0

Slave +

*Loop-timing

High

Float

1

0

Master

High

High

1

1

*To enable Loop-timing in software mode set

SMOD[1:0]=11

78P2352

Dual Channel

OC-3/ STM1-E/ E4 LIU

Reference

Clock

Framer/

Mapper

CKREFP/N

4-bit CMOS TTL

34/39 MHz

4-bit CMOS TTL

PIx[3:0]D

PIxCK

POx[3:0]D

CMIxP/N

TDK

78P2352

34/39 MHz

POxCK

RXxP/N

CMI

CMI

Coax

XFMR

Coax

XFMR

Reference

Clock

Figure 4: Slave Parallel Mode

Framer/

Mapper

CKREFP/N

4-bit CMOS TTL

34/39 MHz

4-bit CMOS TTL

PIx[3:0]D

PTOxCK

POx[3:0]D

CMIxP/N

TDK

78P2352

34/39 MHz

POxCK

RXxP/N

CMI

CMI

Coax

XFMR

Coax

XFMR

Figure 5: Master Parallel Mode

Transmit FIFO Description

Since the reference clock and transmit clock/data go

through different delay paths, it is inevitable that the

phase relationship between the two clocks can vary

in a bounded manner due to the fact that the

absolute delays in the two paths can vary over time.

The transmit FIFO allows long-term clock phase drift

between the Tx clock and system reference clock,

not exceeding +/- 25.6ns, to be handled without

transmit error. If the clock wander exceeds the

specified limits, the FIFO will over or under flow, and

the FERRx register signal will be asserted. This

signal can be used to trigger an interrupt. This

interrupt event is automatically cleared when a FIFO

Reset (FRSTx) pulse is applied, and the FIFO is re-

centered.

Notes:

1) External remote loopbacks (i.e. loopback

within framer) are not possible in

synchronous operation (FIFO enabled)

unless the data is re-justified to be

synchronous to the system reference clock

or the 78P2352 is configured for loop-timing.

2) Most E4 applications will not allow the use of

the dual channel 78P2352 as each channel

is asynchronous to each other. Teridian

recommends using the single channel

78P2351 if one cannot control the E4 timing

reference for each channel.

3) During IC power-up or transmit power-up,

the clocks going to the FIFO may not be

stable and cause the FIFO to overflow or

underflow. As such, the FIFO should be

manually reset using FRST anytime the

transmitter is powered-up.

Page: 6 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

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