A43L0616BV-7UF 查看數據表（PDF） - AMIC Technology

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产品描述 (功能)

比赛名单

A43L0616BV-7UF

512K X 16 Bit X 2 Banks Synchronous DRAM

AMIC Technology 

A43L0616B

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Symbol

Parameter

tRRD(min) Row active to row active delay

tRCD(min) RAS to CAS delay

CAS

Latency

Version

-6

-7

12

14

18

20

Unit

Note

ns

1

ns

1

tRP(min) Row precharge time

tRAS(min)

tRAS(max)

Row active time

tRC(min) Row cycle time

18

20

42

42

100

60

63

ns

1

ns

1

µs

ns

1

tCDL(min) Last data in new col. Address delay

tRDL(min) Last data in row precharge

tBDL(min) Last data in to burst stop

tCCD(min) Col. Address to col. Address delay

3

Number of valid output data

2

1

2

2

1

1

2

1

CLK

2

CLK

2

CLK

2

CLK

CLK

4

CLK

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

PRELIMINARY (May, 2005, Version 0.0)

8

AMIC Technology, Corp.

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