A43L2616AV-6F 查看數據表（PDF） - AMIC Technology

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A43L2616AV-6F

1M X 16 Bit X 4 Banks Synchronous DRAM

AMIC Technology 

A43L2616A

Mode Register Filed Table to Program Modes

Register Programmed with MRS

Address BS0, BS1 A11, A10

A9

A8 A7 A6

A5

A4

A3

A2 A1 A0

Function

RFU

RFU

W.B.L

TM

(Note 1) (Note 2)

CAS Latency

BT

Burst Length

Test Mode

A8 A7

Type

0 0 Mode Register Set

01

Vendor

10

11

Use

Only

Write Burst Length

A9

Length

0

Burst

1

Single Bit

CAS Latency

Burst Type

Burst Length

A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0

BT=1

0 0 0 Reserved 0 Sequential 0 0 0

1

1

001

-

1 Interleave 0 0 1

2

2

010

2

01 0

4

4

011

3

01 1

8

8

1 0 0 Reserved

1 0 0 Reserved Reserved

1 0 1 Reserved

1 0 1 Reserved Reserved

1 1 0 Reserved

1 1 0 Reserved Reserved

1 1 1 Reserved

1 1 1 256(Full) Reserved

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.

Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

PRELIMINARY (November, 2004, Version 0.0)

9

AMIC Technology, Corp.

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