A615308 查看數據表（PDF） - AMIC Technology

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A615308

32K X 8 BIT HIGH SPEED CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise and Fall Time

Input and Output Timing Reference Levels

Output Load

A615308 Series

0V to 3.0V

2 ns

1.5V

See Figures 1 and 2

OUTPUT

ZO=50Ω

RL=50Ω

VT=1.5V

Figure 1. Output Load

Data Retention Characteristics (TA = 0°C to 70°C)

Symbol

Parameter

Min.

VDR VCC for Data Retention

2

ICCDR Data Retention Current

-

Chip Disable to Data Retention

tCDR

Time

0

tR

Operation Recovery Time

tRC*

tRC = Read Cycle Time

+5V

480Ω

I/O

255Ω

5pF*

* Including scope and jig.

Figure 2. Output Load for tCLZ, tOLZ,

tCHZ, tOHZ, tWHZ, and tOW

Max.

5.5

6

-

-

Unit

Conditions

V

CE ≥ VCC - 0.2V

VCC = 2.0V

mA

CE ≥ VCC - 0.2V

VIN ≥ VCC - 0.2V or

VIN ≤ 0.2V

ns

See Retention Waveform

ns

PRELIMINARY (June, 1998, Version 1.1)

8

AMIC Technology, Inc.

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