A6278 查看數據表（PDF） - Allegro MicroSystems

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A6278

Serial-Input Constant-Current Latched LED Drivers with Open LED Detection

Allegro MicroSystems 

A6278 and A6279

Serial-Input Constant-Current Latched

LED Drivers with Open LED Detection

Features and Benefits

▪ 3.0 to 5.5 V logic supply range

▪ Schmitt trigger inputs for improved noise immunity

▪ Power-On Reset (POR)

▪ Up to 90 mA constant-current sinking outputs

▪ LED open circuit detection

▪ Low-power CMOS logic and latches

▪ High data input rate

▪ 20 ns typical staggering delay on the outputs

▪ Internal UVLO and thermal shutdown (TSD) circuitry

Packages:

28 pin MLP/QFN (suffix ET)

16 and 24 pin DIP (suffix A)

16 and 24 pin TSSOP (suffix LP)

16 and 24 pin SOIC (suffix LW)

Description

The A6278 and A6279 devices are specifically designed for

LED display applications. Each of these BiCMOS devices

includes a CMOS shift register, accompanying data latches,

and NPN constant-current sink drivers. The A6278 contains

8 sink drivers, while there are 16 in the A6279.

The CMOS shift register and latches allow direct interfacing

with microprocessor-based systems. With a 3.3 or 5 V logic

supply, typical serial data-input rates can reach up to 25 MHz.

The LED drive current is determined by the user’s selection of

a single resistor. A CMOS serial data output permits cascading

between multiple devices in applications requiring additional

drive lines. Open LED connections can be detected and signaled

back to the host microprocessor through the SERIAL DATA

OUT pin.

Four package styles are provided: an MLP/QFN surface mount,

0.90 mm overall height nominal (A6279 only); a DIP (type A)

for through-hole applications; and for leaded surface-mount, an

SOIC (type LW) and a TSSOP with exposed thermal pad (type

LP). All package styles for the A6278 are electrically identical

to each other, as are the A6279 package styles. All packages

are lead (Pb) free, with 100% matte tin plated leadframes.

Not to scale

LOGIC

SUPPLY

SERIAL

DATA IN

CLOCK

VDD

OUTPUT

ENABLE

LATCH

ENABLE

Functional Block Diagram

UVLO

VDD

Control Logic

Block

Serial - Parallel Shift Register

Latches

SERIAL

DATA OUT

REXT

IO

Regulator

Exposed Pad

(ET and LP packages)

Output Control Drivers and Open Circuit Detector

OUT0 OUT1

GND

OUT7 (A6278)

OUT15 (A6279)

VLED

6278-DS, Rev. 4

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