A62S7316V-70S 查看數據表（PDF） - AMIC Technology

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A62S7316V-70S

128K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise And Fall Time

Input and Output Timing Reference Levels

Output Load

0V to 3.0V

5 ns

1.5V

See Figures 1 and 2

A62S7316 Series

TTL

TTL

CL

30pF

CL

5pF

* Including scope and jig.

* Including scope and jig.

Figure 1. Output Load

Figure 2. Output Load for tCLZ, tOLZ,

tCHZ, tOHZ, tWHZ, and tOW

Data Retention Characteristics (TA = 0°C to 70°C or -25°C to 85°C)

Symbol

Parameter

Min.

Max. Unit

Conditions

VDR

VCC for Data Retention

2.0

3.6

V CE ≥ VCC - 0.2V

ICCDR

Data Retention Current

S-Version

SI-Version

-

5*

-

10**

tCDR

Chip Disable to Data Retention Time

0

-

tR

Operation Recovery Time

TRC

-

* A62S7316-55S/70S

** A62S7316-55SI/70SI

ICCDR: max. 1µA at TA = 0°C to + 40°C

ICCDR: max. 1µA at TA = 0°C to + 40°C

VCC = 2.0V,

µA CE ≥ VCC - 0.2V

VIN ≥ 0V

ns

See Retention Waveform

ns

PRELIMINARY (March, 2001, Version 0.2)

11

AMIC Technology, Inc.

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