A64S06162A 查看數據表（PDF） - AMIC Technology
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A64S06162A
AMIC Technology
A64S06162A Datasheet PDF : 14 Pages
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Preliminary
A64S06162A
MEMORY
16M(1M x 16bit) Normal mode & Page mode with Deep Power Down
Static Random Access Memory
DESCRIPTION
The A64S06162A is a 16Mb high speed, low power Static Random Access Memory(SRAM)
organized as 1,048,576 words by 16 bits and supports Deep Power Down and Page Mode.
The A64S06162A is a Pseudo SRAM based on successfully proven DRAM CELL SRAM which
was specifically developed for cost sensitive, low power computing and communication
applications such as mobile cellular phone handsets, personal digital assistants and other
battery-operated consumer products.
FEATURES
• Standard Asynchronous SRAM Interface with Deep Power Down and Page Mode
• Organization
: 1M x 16Bit
• Power Supply Voltage
: 2.7 ~ 3.3 V
• Page Size
: 4 words
• Page Mode Access (tPAA) : 35ns
• Data Retention Voltage
: 2.4V
• Deep Power Down
: 5uA
• Tri-state Output and TTL Compatible
PRODUCT FAMILY
Product Family
A64S06162A
Operating
Temperature
-40 ~ 85 ℃
Voltage
2.7 ~ 3.3 V
Speed
70
ISB1
(Max)
100uA
IccDR
(Max)
100uA
ICC1
(Max)
2.0mA
Mode
Page
PIN DESCRIPTION
1
2
3
4
5
6
A
/LB /OE A0 A1 A2 /PD
B IO8 /UB A3 A4 /CS IO0
C IO9 IO10 A5 A6 IO1 IO2
D VSS IO11 A17 A7 IO3 VCC
E VCC IO12 VSS A16 IO4 VSS
FUNCTIONAL BLOCK DIAGRAM
Ref. Cont.
DC Generator Circuit
Row
Address
Column
Address
Memory Array
8192 rows
128 x 16 columns
IO0
IO7
IO8
IO15
F IO14 IO13 A14 A15 IO5 IO6
G IO15 A19 A12 A13 /WE IO7
H A18 A8 A9 A10 A11 NC
Note : E3 pin ( VSS) can be remain as a NC
Column Decoder
Control Logic
/CS /PD /OE /WE /UB /LB
Name
/CS
/OE
/WE
A0∼A19
IO0∼IO15
Function
Chip Select Input
Output Enable Input
Write Enable Input
Address Input
Data Input / Output
Name
VCC
VSS
/UB
/LB
/PD
Function
Power
Ground
Upper Byte (IO8∼15)
Lower Byte (IO0∼7)
Deep Power Down
(May, 2005, Version 0.0)
2
AMIC Technology, Corp.
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