PRELIMINARY TECHNICAL DATA
LRCLK
BCLK
DATA
32 BCLKs
SLOT 1
LEFT 0
128 BCLKs
SLOT 2
LEFT 1
SLOT 3
RIGHT 0
SLOT 4
RIGHT 1
MSB MSB–1 MSB–2
Figure 4. ADC Packed Mode 128
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
SLOT 4
SLOT 5
RIGHT 0
SLOT 6
RIGHT 1
SLOT 7
SLOT 8
MSB MSB–1 MSB–2
Figure 5. ADC Packed Mode 256
LRCLK
BCLK
DATA
20 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
128 BCLKs
SLOT 3
LEFT 2
SLOT 4 SLOT 5 SLOT 6
RIGHT 0 RIGHT 1 RIGHT 2
MSB MSB–1 MSB–2
LRCLK
BCLK
DATA
Figure 6. DAC Packed Mode 128
LRCLK
BCLK
DATA
32 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
256 BCLKs
SLOT 3
LEFT 2
SLOT 4 SLOT 5 SLOT 6
RIGHT 0 RIGHT 1 RIGHT 2
MSB
MSB–1
MSB–2
LRCLK
BCLK
DATA
Figure 7. DAC Packed Mode 256
AD1836
REV. PrC
–11–