AD5062 查看數據表（PDF） - Analog Devices
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AD5062 Datasheet PDF : 17 Pages
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AD5062/AD5063
Preliminary Technical Data
TIMING CHARACTERISTICS
(VDD = 2.7-5.5 V; all specifications TMIN to TMAX unless otherwise noted)
Parameter
t13
t2
t3
t4
t5
t6
t7
t8
t9
Limit1
33
13
12
13
5
4.5
0
33
13
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Rising Edge to next SCLK Fall
Ignore
.
NOTES
1All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2See Figure 1.
3Maximum SCLK frequency is 30 MHz.
Specifications subject to change without notice.
Figure 1. Timing Diagram
Rev. Pr B | Page 4 of 17
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