AD5066(RevPrB) 查看數據表（PDF） - Analog Devices

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AD5066
(Rev.:RevPrB)

Fully Accurate 16-Bit UnBuffered VOUT DAC SPI Interface 2.7 V to 5.5 V in a TSSOP

Analog Devices 

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5066

Figure 4. 16-Lead TSSOP (RU-16)

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This

allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.

2

SYNC

3

VDD

4

VREFB

5

VREFA

6

VOUTA

7

VOUTC

8

POR

9

VREFC

10

CLR

11

VREFD

12

VOUTD

13

VOUTB

14

GND

15

DIN

16

SCLK

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on

the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge

of SYNC acts as an interrupt and the write sequence is ignored by the device.

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled

with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

Dac B reference input .This is the reference voltage input pin for Dac B.

Dac A reference input .This is the reference voltage input pin for Dac A.

Unbuffered analog output voltage from DAC A.

Unbuffered analog output voltage from DAC C.

Power-on Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to VDD powers up

the part to midscale.

Dac B reference input .This is the reference voltage input pin for Dac C.

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are

ignored. When CLR is activated, the input register and the DAC register are updated with the data

contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V.

Dac A reference input .This is the reference voltage input pin for Dac D.

Unbuffered analog output voltage from DAC D.

Unbuffered analog output voltage from DAC B.

Ground Reference Point for All Circuitry on the Part.

Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input.

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at rates of up to 50 MHz.

Rev. PrB | Page 9 of 20

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