AD5546 查看數據表（PDF） - Analog Devices

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AD5546

Current Output, Parallel Input, 16-/14-Bit Multiplying DACs with 4-Quadrant Resistors

Analog Devices 

AD5546/AD5556

Pin No.

15

16

17

18

19

20–27

28

Mnemonic

LDAC

WR

MSB

RS

GND

D13 to D6

VDD

Description

Digital Input Load DAC Control. Signal level must be ≤ VDD + 0.3 V.

Write Control Digital Input in Active Low. Transfers shift-register data to DAC register on rising edge. Signal level

must be ≤ VDD + 0.3 V.

Power On Reset State. MSB = 0 resets at zero-scale, MSB = 1 resets at midscale. Signal level must be ≤ VDD + 0.3 V.

Reset in Active Low. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1. Signal level must be

≤ VDD + 0.3 V.

Analog and Digital Grounds.

Digital Input Data Bits D13 to D6. Signal level must be ≤ VDD + 0.3 V.

Positive power supply input. Specified range of operation: 2.7 V to 5.5 V.

tWR

WR

DATA

LDAC

RS

tDS

tDH

tLWD

tLDAC

tRS

Figure 5. AD5546/AD5556 Timing Diagram

Table 5. AD5546 Parallel Input Data Format

MSB

LSB

Bit Position

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Data Word

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 6. AD5556 Parallel Input Data Format

MSB

Bit Position

B13 B12 B11

Data Word

D13 D12 D11

B10 B9

D10 D9

B8 B7 B6

D8 D7 D6

B5 B4 B3

D5 D4 D3

LSB

B2 B1 B0

D2 D1 D0

Table 7. Control Inputs

RS WR LDAC Register Operation

0X

X

Reset output to 0, with MSB pin = 0. Midscale with MSB pin = 1.

10

0

Load input register with data bits.

11

1

Load DAC register with the contents of the input register.

10

1

Input and DAC registers are transparent.

1

When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on

the falling edge of the pulse, and then loaded into the DAC register on the rising edge of the pulse.

11

0

No register operation.

Rev. 0 | Page 7 of 16

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