AD5678BRUZ-2 查看數據表（PDF） - Analog Devices

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AD5678BRUZ-2

4 × 12-Bit and 4 × 16-Bit Octal DAC with On-Chip Reference in 14-Lead TSSOP

Analog Devices 

AD5678

THEORY OF OPERATION

D/A SECTION

The AD5678 DAC is fabricated on a CMOS process. The archi-

tecture consists of a string of DACs followed by an output buffer

amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C

reference with an internal gain of 2. Figure 45 shows a block

diagram of the DAC architecture.

VDD

DAC REGISTER

REF (+)

RESISTOR

STRING

REF (–)

GND

Figure 45. DAC Architecture

OUTPUT

AMPLIFIER

(GAIN = +2)

VOUT

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

VOUT

= VREFIN

×

⎜⎝⎛

D

2N

⎟⎠⎞

the ideal output voltage when using an internal reference is

given by

VOUT

= 2 ×VREFOUT

×

⎜⎝⎛

D

2N

⎟⎠⎞

where:

D = decimal equivalent of the binary code that is loaded to the

DAC register.

0 to 4,095 for AD5678 DAC C, D, E, F (12 bits).

0 to 65,535 for AD5678 DAC A, B, G, H (16 bits).

N = the DAC resolution.

RESISTOR STRING

The resistor string section is shown in Figure 46. It is simply a

string of resistors, each of value R. The code loaded into the

DAC register determines at which node on the string the

voltage is tapped off to be fed into the output amplifier. The

voltage is tapped off by closing one of the switches connecting

the string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

R

R

R

TO OUTPUT

AMPLIFIER

R

R

Figure 46. Resistor String

INTERNAL REFERENCE

The AD5678 has an on-chip reference with an internal gain of

2. The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full-

scale output of 2.5 V. The AD5678-2 has a 2.5 V 5 ppm/°C

reference, giving a full-scale output of 5 V. The on-board

reference is off at power-up, allowing the use of an external

reference. The internal reference is enabled via a write to a

control register. See Table 7.

The internal reference associated with each part is available at

the VREFOUT pin. A buffer is required if the reference output is

used to drive external loads. When using the internal reference,

it is recommended that a 100 nF capacitor be placed between

the reference output and GND for reference stability.

Individual channel power-down is not supported while using

the internal reference.

Rev. C | Page 20 of 28

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