CDB4228A 查看數據表（PDF） - Cirrus Logic
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CDB4228A Datasheet PDF : 32 Pages
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CS4228A
SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: Logic 0 = 0V, Logic 1 = VL)
Parameter
SPI Mode (SDOUT > 47 kΩ to GND)
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol
Min
fsck
-
tcsh
1.0
tcss
20
tscl
66
tsch
66
tdsu
40
(Note 18)
tdh
15
(Note 19)
tr2
(Note 19)
tf2
Max
Units
6
MHz
µs
ns
ns
ns
ns
ns
30
ns
100
ns
Notes: 18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For FSCK < 1 MHz
CS
t css
t scl t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu t dh
Figure 3. SPI Control Port Timing
10
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