AD73411 查看數據表（PDF） - Analog Devices
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AD73411 Datasheet PDF : 36 Pages
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POWER CONSUMPTION
Parameter
Typ
Max
SE
AFE SECTION
ADC Only On
7
8
1
ADC and DAC On
11
12.5
1
REFCAP Only On
0.65
1.00
0
REFCAP and
2.7
3.8
0
REFOUT Only On
All AFE Sections Off
0.6
0.75
0
All AFE Sections Off
5 µA
30 µA
0
DSP SECTION
Idle Mode
6.4
Dynamic
43
NOTES
The above values are in mA and are typical values unless otherwise noted.
Specifications subject to change without notice.
MCLK On
Yes
Yes
No
No
Yes
No
TIMING CHARACTERISTICS–AFE SECTION
Parameter
Limit
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
Specifications subject to change without notice.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
AD73411
Test Conditions
REFOUT Disabled
REFOUT Disabled
REFOUT Disabled
MCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
Description
See Figure 1
16.384 MHz AMCLK Period
MCLK Width High
MCLK Width Low
See Figures ? and ?
SCLK Period (SCLK = AMCLK)
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
REV. 0
–5–
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