AD7266 查看數據表（PDF） - Analog Devices
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AD7266 Datasheet PDF : 20 Pages
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Preliminary Technical Data
AD7357
TIMING SPECIFICATIONS
VDD = 2.5 V ± 10%, VDRIVE = 2.25 V to 3.6 V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted.
Table 3.
Parameter
fSCLK
tCONVERT
tQUIET
t2
t32
t42, 3
t5
t6
t72
t8
t9
t102
Latency
Limit at TMIN, TMAX
50
80
t2 + 15 × tSCLK
5
5
6
Unit
kHz min
MHz max
ns max
ns min
ns min
ns max
12.5
ns max
11
ns max
9.5
ns max
9
ns max
5
ns min
5
ns min
3.5
ns min
9.5
ns max
5
ns min
4.5
ns min
9.5
ns max
1 conversion latency
Description
tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
CS to SCLK setup time
Delay from CS until SDATAA and SDATAB are three-state disabled
Data access time after SCLK falling edge
1.8 V ≤ VDRIVE < 2.25 V
2.25 V ≤ VDRIVE < 2.75 V
2.75 V ≤ VDRIVE < 3.3 V
3.3 V ≤ VDRIVE ≤ 3.6 V
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
CS rising edge to SDATAA, SDATAB, high impedance
CS rising edge to falling edge pulse width
SCLK falling edge to SDATAA, SDATAB, high impedance
SCLK falling edge to SDATAA, SDATAB, high impedance
1 Temperature ranges are as follows: Y grade: −40°C to +125°C, B grade: −40°C to +85°C.
2 Specified with a load capacitance of 10 pF on SDATAA and SDATAB.
3 The time required for the output to cross 0.4 V or 2.4 V.
Rev. PrF | Page 5 of 20
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