AD7401YRWZ-REEL 查看數據表（PDF） - Analog Devices

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AD7401YRWZ-REEL

Isolated Sigma-Delta Modulator

Analog Devices 

AD7401

always @ (posedge word_clk or posedge reset)

if(reset)

begin

acc3_d2 <= 0;

diff1_d <= 0;

diff2_d <= 0;

diff1 <= 0;

diff2 <= 0;

diff3 <= 0;

end

else

begin

diff1 <= acc3 - acc3_d2;

diff2 <= diff1 - diff1_d;

diff3 <= diff2 - diff2_d;

acc3_d2 <= acc3;

diff1_d <= diff1;

diff2_d <= diff2;

end

/* Clock the Sinc output into an output

register

WORD_CLK

DIFF3

DATA

Figure 28. Clocking Sinc Output into an Output Register

WORD_CLK = output word rate

*/

always @ (posedge word_clk)

begin

DATA[15] <= diff3[23];

DATA[14] <= diff3[22];

DATA[13] <= diff3[21];

DATA[12] <= diff3[20];

DATA[11] <= diff3[19];

DATA[10] <= diff3[18];

DATA[9]

DATA[8]

DATA[7]

DATA[6]

DATA[5]

DATA[4]

DATA[3]

DATA[2]

DATA[1]

DATA[0]

<= diff3[17];

<= diff3[16];

<= diff3[15];

<= diff3[14];

<= diff3[13];

<= diff3[12];

<= diff3[11];

<= diff3[10];

<= diff3[9];

<= diff3[8];

end

endmodule

90

SINC3

80

70

SINC2

60

50

40

SINC1

30

20

10

0

1

10

100

1k

DECIMATION RATE

Figure 29. SNR vs. Decimation Rate for Different Filter Types

Figure 29 shows a plot of SNR performance vs. decimation rate

with different filter types. Note that for a given bandwidth

requirement, a higher MCLKIN frequency can allow for higher

decimation rates to be used resulting in higher SNR

performance.

Rev. A | Page 16 of 20

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