AD7484 查看數據表（PDF） - Analog Devices

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AD7484

3 MSPS, 14-Bit SAR ADC

Analog Devices 

AD7484

CONVST

BUSY

CS

t1

t2

RD

D[14:0]

tCONV

tACQ

tQUIET

t14

t3

t15

t8

t4

t7

DATA VALID

Figure 29. Parallel Mode READ Cycle

CONVST

CS

RD

WRITE

D[14:0]

t12

t13

t9

t10

t11

OFFSET DATA

Figure 30. Parallel Mode WRITE Cycle

CONVST

BUSY

D[14:0]

t1

N

t2

tCONV

N+1

DATA N – 1

t6

DATA N

Figure 31. Parallel Mode 1 READ Cycle

CONVST

BUSY

D[14:0]

t1

N

t2

tCONV

N+1

t5

DATA N – 1

Figure 32. Parallel Mode 2 READ Cycle

DATA N

Rev. C | Page 18 of 20

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