AD7610 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

比赛名单

AD7610

16-Bit, 250 kSPS, Unipolar/Bipolar Programmable Input PulSAR® ADC

Analog Devices 

AD7610

Table 4. Serial Clock Timings in Master Read After Convert Mode

DIVSCLK[1]

DIVSCLK[0]

Symbol

SYNC to SDCLK First Edge Delay Minimum

t18

Internal SDCLK Period Minimum

t19

Internal SDCLK Period Maximum

t19

Internal SDCLK High Minimum

t20

Internal SDCLK Low Minimum

t21

SDOUT Valid Setup Time Minimum

t22

SDOUT Valid Hold Time Minimum

t23

SDCLK Last Edge to SYNC Delay Minimum

t24

BUSY High Width Maximum

t28

0

0

1

1

0

1

0

1

Unit

3

20

20

20

ns

30

60

120

240

ns

45

90

180

360

ns

15

30

60

120

ns

10

25

55

115

ns

4

20

20

20

ns

5

8

35

90

ns

5

7

35

90

ns

2.25

3.00

4.40

7.30

μs

1.6mA

IOL

TO OUTPUT

PIN CL

60pF

1.4V

500µA

IOH

NOTES

1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND

SDOUT ARE DEFINED WITH A MAXIMUM LOAD

CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.

Figure 2. Load Circuit for Digital Interface Timing,

SDOUT, SYNC, and SCLK Outputs, CL = 10 pF

0.8V

tDELAY

2V

0.8V

2V

tDELAY

2V

0.8V

Figure 3. Voltage Reference Levels for Timing

Rev. 0 | Page 6 of 32

Share Link: