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AD7674 查看數據表(PDF) - Analog Devices

零件编号
产品描述 (功能)
比赛名单
AD7674
ADI
Analog Devices ADI
AD7674 Datasheet PDF : 23 Pages
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AD7665
TIMING SPECIFICATIONS (continued)
Parameter
Symbol Min
Typ
Max
Refer to Figures 17 and 18 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
t14
CS LOW to Internal SCLK Valid Delay
t15
CS LOW to SDOUT Delay
t16
CNVST LOW to SYNC Delay (Read during Convert)
t17
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay3
Internal SCLK Period3
Internal SCLK HIGH3
t18
4
t19
25
t20
15
Internal SCLK LOW3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
t21
9.5
t22
4.5
t23
2
SCLK Last Edge to SYNC Delay3
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert3
CNVST LOW to SYNC Asserted Delay
t24
3
t25
t26
t27
t28
t29
(Warp Mode/Normal Mode/Impulse Mode)
Master Serial Read after Convert
SYNC Deasserted to BUSY LOW Delay
t30
10
10
10
25/275/525
40
10
10
10
See Table II
0.75/1/1.25
25
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time
t31
5
External SCLK Active Edge to SDOUT Delay
t32
3
16
SDIN Setup Time
SDIN Hold Time
External SCLK Period
t33
5
t34
5
t35
25
External SCLK HIGH
External SCLK LOW
t36
10
t37
10
NOTES
1In Warp Mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time.
2In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum.
3In Serial Master Read During Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
t18
Internal SCLK Period Minimum
t19
Internal SCLK Period Maximum
t19
Internal SCLK HIGH Minimum
t20
Internal SCLK LOW Minimum
t21
SDOUT Valid Setup Time Minimum
t22
SDOUT Valid Hold Time Minimum
t23
SCLK Last Edge to SYNC Delay Minimum
t24
BUSY HIGH Width Maximum (Warp)
t28
BUSY HIGH Width Maximum (Normal)
t28
BUSY HIGH Width Maximum (Impulse)
t28
0
0
1
1
0
1
0
1
4
20
20
20
25
50
100
200
40
70
140
280
15
25
50
100
9.5
24
49
99
4.5
22
22
22
2
4
30
90
3
60
140
300
1.5
2
3
5.25
1.75
2.25
3.25
5.5
2
2.5
3.5
5.75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
–4–
REV. C

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