AD7843 查看數據表（PDF） - Analog Devices
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AD7843 Datasheet PDF : 20 Pages
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AD7843
Parameter
POWER REQUIREMENTS
VCC (Specified Performance)
ICC5
Normal Mode (fSAMPLE = 125 kSPS)
Normal Mode (fSAMPLE = 12.5 kSPS)
Normal Mode (Static)
Shutdown Mode (Static)
Power Dissipation5
Normal Mode (fSAMPLE = 125 kSPS)
Shutdown
AD7843A1
2.7/3.6
380
170
150
1
1.368
3.6
1 Temperature range as follows: A Version: −40°C to +85°C.
2 See the Terminology section.
3 Guaranteed by design.
4 Sample tested @ 25°C to ensure compliance.
5 See the Power vs. Throughput Rate section.
Unit
V min/max
µA max
µA typ
µA typ
µA max
mW max
µW max
Test Conditions/Comments
Functional from 2.2 V to 5.25 V
Digital I/Ps = 0 V or VCC
VCC = 3.6 V, 240 µA typ
VCC = 2.7 V, fDCLK = 200 kHz
VCC = 3.6 V
VCC = 3.6 V
VCC = 3.6 V
TIMING SPECIFICATIONS
TA = TMIN to TMAX, unless otherwise noted; VCC = 2.7 V to 3.6 V, VREF = 2.5 V.
Table 2. Timing Specifications1
Parameter
fDCLK2
Limit at TMIN, TMAX
10
2
tACQ
1.5
t1
10
t2
60
t3
60
t4
200
t5
200
t6
60
t7
10
t8
10
t93
200
t10
0
t11
200
t124
200
Unit
kHz min
MHz max
µs min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns max
Description
Acquisition time
CS falling edge to First DCLK rising edge
CS falling edge to BUSY three-state disabled
CS falling edge to DOUT three-state disabled
DCLK high pulse width
DCLK low pulse width
DCLK falling edge to BUSY rising edge
Data setup time prior to DCLK rising edge
Data valid to DCLK hold time
Data access time after DCLK falling edge
CS rising edge to DCLK ignored
CS rising edge to BUSY high impedance
CS rising edge to DOUT high impedance
1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.6 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.4 V or 2.0 V.
4 t12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t12, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
IOL
TO
OUTPUT
PIN
CL
50pF
1.6V
200µA
IOH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. B | Page 4 of 20
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