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AD7923(Rev0) 查看數據表(PDF) - Analog Devices

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产品描述 (功能)
比赛名单
AD7923 Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD7923
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
AVDD
VDRIVE
IDD4
During Conversion
Normal Mode (Static)
Normal Mode (Operational) fSAMPLE = 200 kSPS
Using Auto Shutdown Mode fSAMPLE = 200 kSPS
Auto Shutdown (Static)
Full Shutdown Mode
Power Dissipation4
Normal Mode (Operational) fSAMPLE = 200 kSPS
Auto Shutdown (Static)
Full Shutdown Mode
NOTES
1Temperature ranges as follows: B Version: –40C to +85C.
2See Terminology section.
3Sample tested @ 25C to ensure compliance.
4See Power versus Throughput Rate section.
Specifications subject to change without notice.
B Version1
800
300
300
200
2.7/5.25
2.7/5.25
2.7
2.0
600
1.5
1.2
900
650
0.5
0.5
7.5
3.6
2.5
1.5
2.5
1.5
Unit
Test Conditions/Comments
ns max
ns max
ns max
kSPS max
16 SCLK Cycles with SCLK at 20 MHz
Sine Wave Input
Full-Scale Step Input
See Serial Interface Section
V min/max
V min/max
mA max
mA max
mA typ
mA max
mA max
mA typ
mA typ
mA max
mA max
Digital I/Ps = 0 V or VDRIVE
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
AVDD = 2.7 V to 5.25 V, SCLK On or Off
AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz
AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz
AVDD = 4.75 V to 5.25 V, fSAMPLE = 200 kSPS
AVDD = 2.7 V to 3.6 V, fSAMPLE = 200 kSPS
SCLK On or Off (20 nA typ)
SCLK On or Off (20 nA typ)
mW max
mW max
mW max
mW max
mW max
mW max
AVDD = 5 V, fSCLK = 20 MHz
AVDD = 3 V, fSCLK = 20 MHz
AVDD = 5 V
AVDD = 3 V
AVDD = 5 V
AVDD = 3 V
REV. 0
–3–

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