AD7927 查看數據表（PDF） - Analog Devices

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AD7927

8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SCLK 1

DIN 2

CS 3

AGND 4

AVDD 5

AVDD 6

REFIN 7

AGND 8

VIN7 9

VIN6 10

20 AGND

19 VDRIVE

AD7927 18 DOUT

TOP VIEW 17 AGND

(Not to Scale) 16 VIN0

15 VIN1

14 VIN2

13 VIN3

12 VIN4

11 VIN5

Figure 3. 20-Lead TSSOP Pin Configuration

AD7927

Table 4. Pin Function Descriptions

Pin No.

Mnemonic Description

1

SCLK

Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is

also used as the clock source for the AD7927 conversion process.

2

DIN

Data In. Logic input. Data to be written to the AD7927 control register is provided on this input and is clocked

into the register on the falling edge of SCLK (see the Control Register section).

3

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the

AD7927 and framing the serial data transfer.

4, 8, 17, 20 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7927. All analog input signals

and any external reference signal should be referred to this AGND voltage. All AGND pins should be

connected together.

5, 6

AVDD

Analog Power Supply Input. The AVDD range for the AD7927 is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN

range, AVDD should be from 4.75 V to 5.25 V.

7

REFIN

Reference Input for the AD7927. An external reference must be applied to this input. The voltage range for

the external reference is 2.5 V ±1% for specified performance.

16 to 9

VIN0 to VIN7

Analog Input 0 through Analog Input 7. Eight single-ended analog input channels that are multiplexed into

the on-chip track-and-hold. The analog input channel to be converted is selected by using the address bits

(ADD2 through ADD0) of the control register. ADD2 through ADD0, in conjunction with the SEQ and

SHADOW bits, allow the sequencer to be programmed. The input range for all input channels can extend

from 0 V to REFIN or 0 V to 2 × REFIN, as selected via the RANGE bit in the control register. Any unused input

channels should be connected to AGND to avoid noise pickup.

18

DOUT

Data Out. Logic output. The conversion result from the AD7927 is provided on this output as a serial data

stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7927

consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to,

followed by the 12 bits of conversion data (MSB first). The output coding may be selected as straight binary or

twos complement via the CODING bit in the control register.

19

VDRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of

the AD7927 operates.

Rev. D | Page 7 of 28

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