AD7949 查看數據表（PDF） - Analog Devices
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AD7949 Datasheet PDF : 32 Pages
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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD7949
VDD 1
REF 2
REFIN 3
GND 4
GND 5
AD7949
TOP VIEW
(Not to Scale)
15 VIO
14 SDO
13 SCK
12 DIN
11 CNV
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SYSTEM
GROUND PLANE.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1
1, 20
VDD
P
2
REF
AI/O
3
REFIN
AI/O
4, 5
GND
P
6 to 9 IN4 to IN7
AI
10
COM
AI
11
CNV
DI
12
DIN
DI
13
SCK
DI
14
SDO
DO
15
VIO
P
16 to 19 IN0 to IN3
AI
21
Exposed Pad NC
(EPAD) (EPAD)
Description
Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with
10 μF and 100 nF capacitors.
When using the internal reference for 2.5 V output, the minimum should be 3.0 V.
When using the internal reference for 4.096 V output, the minimum should be 4.5 V.
Reference Input/Output. See the Voltage Reference Output/Input section.
When the internal reference is enabled, this pin produces a selectable system reference = 2.5 V or 4.096 V.
When the internal reference is disabled and the buffer is enabled, REF produces a buffered version
of the voltage present on the REFIN pin (4.096 V maximum), useful when using low cost, low power
references.
For improved drift performance, connect a precision reference to REF (0.5 V to VDD).
For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as
close to REF as possible. See the Reference Decoupling section.
Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section.
When using the internal reference, the internal unbuffered reference voltage is present and needs
decoupling with a 0.1 μF capacitor.
When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered
to the REF pin as described above.
Power Supply Ground.
Channel 4 through Channel 7 Analog Inputs.
Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of
0 V or VREF/2 V.
Convert Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held
high, the busy indictor is enabled.
Data Input. This input is used for writing to the 14-bit configuration register. The configuration
register can be written to during and after conversion.
Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in
an MSB first fashion.
Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar
modes, conversion results are straight binary; in bipolar modes, conversion results are twos
complement.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5
V, 3 V, or 5 V).
Channel 0 through Channel 3 Analog Inputs.
The exposed pad is not connected internally. For increased reliability of the solder joints, it is
recommended that the pad be soldered to the system ground plane.
1AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
Rev. F | Page 9 of 32
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