AD80066
ANALOG
INPUTS
CDSCLK1
tAD
tC1
PIXEL n (A, B, C)
tAD
tC2C1
PIXEL (n + 1)
tPRA
PIXEL (n + 2)
CDSCLK2
tC1C2
tC2
tC2ADF
ADCCLK
tADCCLK
tADC2
tC2ADR
OUTPUT
DATA
(D[7:0])
tADCCLK
tOD
A(n – 2) B(n – 2) B(n – 2) C(n – 2) C(n – 2) A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n – 1) A(n) A(n) B(n) B(n)
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW HIGH LOW HIGH LOW HIGH
BYTE BYTE BYTE BYTE BYTE BYTE
Figure 4. 3-Channel CDS Mode Timing
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
PIXEL n
tAD
tAD
tC1
tC1C2
tC2
tADC2
tC2ADR
tC2C1
tC2ADF
PIXEL (n + 1)
tPRA
PIXEL (n + 2)
tADCCLK
CH 1 (n – 2)
HIGH
BYTE
LOW
BYTE
tADCCLK
CH 2 (n – 2)
CH 1 (n – 1)
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
Figure 5. 2-Channel CDS Mode Timing
CH 2 (n – 1)
HIGH
BYTE
LOW
BYTE
CH 1 (n)
HIGH
BYTE
LOW
BYTE
Rev. A | Page 6 of 20