AD9142 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
比赛名单
AD9142 Datasheet PDF : 65 Pages
| |||
Data Sheet
AD9142
DAC LATENCY SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, FIFO level is set to 4 (half of the FIFO depth), unless
otherwise noted.
Table 3.
Parameter
WORD INTERFACE MODE
2× Interpolation
4× Interpolation
8× Interpolation
BYTE INTERFACE MODE
2× Interpolation
4× Interpolation
8× Interpolation
INDIVIDUAL FUNCTION BLOCKS
Modulation
Fine
Coarse
Inverse Sinc
Phase Compensation
Gain Compensation
Test Conditions/Comments
Fine/coarse modulation, inverse sinc, gain/phase compensation off
Fine/coarse modulation, inverse sinc, gain/phase compensation off
Min Typ Max Unit
134
DACCLK cycles
244
DACCLK cycles
481
DACCLK cycles
145
DACCLK cycles
271
DACCLK cycles
506
DACCLK cycles
17
DACCLK cycles
10
DACCLK cycles
20
DACCLK cycles
12
DACCLK cycles
16
DACCLK cycles
LATENCY VARIATION SPECIFICATIONS1
Table 4.
Parameter
DAC LATENCY VARIATION
SYNC Off
SYNC On
Min
Typ
Max
Unit
2
DACCLK cycles
1
DACCLK cycles
1 DAC latency is defined as the elapsed time from a data sample clocked at the input to the AD9142 until the analog output begins to change.
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 5.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 737.28 MSPS
BW = 125 MHz
BW = 270 MHz
fDAC = 983.04 MSPS
BW = 360MHz
fDAC = 1228.8 MSPS
BW = 200MHz
BW = 500MHz
fDAC = 1474.56 MSPS
BW = 737MHz
BW = 400MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 737.28 MSPS
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
fDAC = 1474.56 MSPS
Test Conditions/Comments
−14 dBFS single tone
fOUT = 200 MHz
fOUT = 200 MHz
fOUT = 280 MHz
fOUT = 10 MHz
fOUT = 280 MHz
−6 dBFS each tone
fOUT = 200 MHz
fOUT = 200 MHz
fOUT = 280 MHz
fOUT = 10 MHz
fOUT = 280 MHz
Min Typ Max Unit
85
dBc
80
dBc
85
dBc
85
dBc
75
dBc
85
dBc
80
dBc
80
dBc
82
dBc
80
dBc
85
dBc
79
dBc
Rev. 0 | Page 7 of 64
Share Link: 