AD9146(Rev0) 查看數據表（PDF） - Analog Devices

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AD9146
(Rev.:Rev0)

Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

AD9146

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Companion Products ....................................................................... 1

Typical Signal Chain......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

Digital Specifications ................................................................... 5

Digital Input Data Timing Specifications ................................. 5

AC Specifications.......................................................................... 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

Serial Port Operation ................................................................. 15

Data Format ................................................................................ 15

Serial Port Pin Descriptions...................................................... 15

Serial Port Options ..................................................................... 16

Device Configuration Register Map and Descriptions ......... 17

LVDS Input Data Ports .................................................................. 27

Byte Interface Mode ................................................................... 27

Nibble Interface Mode ............................................................... 27

FIFO Operation .......................................................................... 27

Interface Timing ......................................................................... 30

Digital Datapath.............................................................................. 31

Premodulation ............................................................................ 31

Interpolation Filters ................................................................... 31

Datapath Configuration ............................................................ 33

Determining Interpolation Filter Modes ................................ 33

Coarse Modulation Mixing Sequences.................................... 34

Quadrature Phase Correction................................................... 34

DC Offset Correction ................................................................ 34

Inverse Sinc Filter ....................................................................... 35

DAC Input Clock Configurations ................................................ 36

Driving the DACCLK and REFCLK Inputs ........................... 36

Direct Clocking .......................................................................... 36

Clock Multiplication .................................................................. 36

PLL Settings ................................................................................ 37

Configuring the VCO Tuning Band ........................................ 37

Analog Outputs............................................................................... 38

Transmit DAC Operation.......................................................... 38

Auxiliary DAC Operation ......................................................... 39

Interfacing to Modulators ......................................................... 40

Baseband Filter Implementation .............................................. 40

Driving the ADL5375-15 .......................................................... 40

Reducing LO Leakage and Unwanted Sidebands .................. 41

Device Power Management........................................................... 42

Power Dissipation....................................................................... 42

Tx Enable..................................................................................... 42

Temperature Sensor ................................................................... 43

Multichip Synchronization............................................................ 44

Synchronization with Clock Multiplication ............................... 44

Synchronization with Direct Clocking.................................... 45

Data Rate Mode Synchronization ............................................ 45

FIFO Rate Mode Synchronization ........................................... 46

Additional Synchronization Features ...................................... 47

Interrupt Request Operation ........................................................ 48

Interrupt Service Routine.......................................................... 48

Interface Timing Validation .......................................................... 49

SED Operation............................................................................ 49

SED Example .............................................................................. 50

Example Start-Up Routine ............................................................ 51

Device Configuration ................................................................ 51

Derived PLL Settings ................................................................. 51

Start-Up Sequence...................................................................... 51

Outline Dimensions ....................................................................... 52

Ordering Guide .......................................................................... 52

REVISION HISTORY

4/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 52

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