AD9230-210(Rev0) 查看數據表（PDF） - Analog Devices
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AD9230-210
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD9230-210 Datasheet PDF : 32 Pages
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AD9230
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
(Differential)
Input Capacitance
LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current (SDIO)
Logic 0 Input Current (SDIO)
Logic 1 Input Current
(SCLK, PDWN, CSB, RESET)
Logic 0 Input Current
(SCLK, PDWN, CSB, RESET)
Input Capacitance
LOGIC OUTPUTS2
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
AD9230-170
Min
Typ Max
AD9230-210
Min
Typ Max
AD9230-250
Min
Typ Max
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD −
0.3
AVDD +
1.6
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
16
20 24
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD −
0.3
AVDD +
1.6
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
16
20 24
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD −
0.3
AVDD +
1.6
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
16
20
24
4
4
4
0.8 ×
VDD
0.2 ×
AVDD
0
−60
55
0
4
0.8 ×
VDD
0.8 ×
VDD
0.2 ×
AVDD
0
−60
55
0
4
0.2 ×
AVDD
0
−60
50
0
4
247
1.125
454
247
454
247
1.375 1.125
1.375 1.125
Twos complement, Gray code, or offset binary (default)
454
1.375
Unit
V
V p-p
V
V
V
V
μA
μA
kΩ
pF
V
V
μA
μA
μA
μA
pF
mV
V
1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
2 LVDS RTERMINATION = 100 Ω.
Rev. 0 | Page 5 of 32
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